1. Field of the Invention
The present invention relates to a method and an apparatus for the treatment of a semiconductor wafer by means of an oxidation with locally different oxidation rates.
2. Background Art
A semiconductor wafer, in particular a single-crystal silicon wafer for use in the semiconductor industry, has to have a high flatness, in particular in order to take account of the requirements for the production of integrated circuits. A generally recognized rule of thumb states that the SFQRmax value of a semiconductor wafer must be no greater than the line width of the components which are intended to be produced on the semiconductor wafer. In order to be able to integrate the maximum possible number of circuits, the required flatness must moreover be ensured as close as possible to the edge of the front side, where the front side is defined as the side on which the components are intended to be produced. This means that the measurement of the flatness is to be carried out with a very small edge exclusion and the specified flatness values need to be satisfied not only for the so-called full sites but also for the partial sites. In this respect, full sites are all surface elements on which complete components can be produced, whereas partial sites are the surface elements at the edge of the wafer on which there is insufficient space for complete components.
In defining the flatness of semiconductor wafers, the SEMI standard M1-94 draws a distinction between global flatness and local flatness. The global flatness relates to the entire wafer surface minus an edge exclusion which is to be defined. It is described by the GBIR (“global backsurface referenced ideal plane/range”, or range of the positive and negative deviation from a back surface-referenced ideal plane for the entire front side of the semiconductor wafer), which corresponds to the formerly customary term TTV (“total thickness variation”). The local flatness relates to a limited area on the semiconductor wafer, which generally corresponds to the area of the component to be established thereon. It is often expressed as the SFQR (“site front surface referenced least squares/range”, or range of the positive and negative deviation from a front side, defined by error square minimization, for an area of defined dimensions). The variable SFQRmax indicates the highest SFQR value for all the component areas on a specific semiconductor wafer. In the case of SFQR, it is always necessary to indicate the area to which the value indicated relates, for example an area of 26×8 mm2 in accordance with the ITRS roadmap.
A further flatness parameter is the so-called nanotopography. This is defined as the peak-to-valley deviation in a predefined surface element, e.g. 2×2 mm2. The nanotopography is measured using measuring units such as ADE CR 83 SQM, ADE PhaseShift Nanomapper or KLA Tencor SNT.
The flatness in the edge region of the semiconductor wafer is crucially influenced by the so-called “Edge Roll off”. “A New Method for the Precise Measurement of Wafer Roll off of Silicon Polished Wafer”, Jpn. J. Appl. Phys., vol. 38 (1999), pages 38-39, describes the measurement of the “wafer roll off”, or edge roll off. The edge roll off can occur both on the front side and on the rear side of the semiconductor wafer. It can have a significant influence on the SFQR values of the surface elements located at the edge of the wafer. An edge roll off is disturbing in particular in the case of semiconductor wafers which, for example to produce SOI wafers, are connected (bonded) to a further semiconductor wafer, since the edge roll off of the wafer surfaces which are to be connected to one another has a great influence on the bonding quality at the edge of the wafer.
At the present time, semiconductor wafers which serve as substrates for the production of microelectronic components are generally produced according to the following conventional process sequence: sawing, lapping and/or grinding, wet-chemical etching, stock removal polishing and mirror polishing. It has been found that this process sequence is unable to ensure the flatnesses required for the ever-decreasing line widths.
In EP798766A1, a vapor phase etching step according to the PACE (“plasma assisted chemical etching”) method followed by a heat treatment is inserted between stock removal polishing and mirror polishing in the conventional process sequence, in order to improve the flatness of the semiconductor wafer. It is shown on the basis of the processing of silicon wafers having a diameter of 200 mm that the process sequence described allows GBIR results of 0.2-0.3 μm. The document does not give any local flatness data. Furthermore, it does not state the size of the edge exclusion used for the flatness measurement.
EP961314A1 specifies a similar method, in which, after sawing, grinding, PACE and mirror polishing, GBIR values of at best 0.14 μm and SFQRmax values of at best 0.07 μm are achieved.
The PACE method, as proposed in EP961314A1, leads to a deterioration in the roughness of a polished wafer, which can be partially reduced by an additional hydrophobizing step directly before the PACE. PACE has to be carried out in vacuo, which makes the process complex in terms of the equipment technology. Moreover, the semiconductor wafer is contaminated with the decomposition products of the gases used for etching, which necessitates an additional cleaning step, as described in EP1100117A2. Furthermore, this process is not carried out over the entire surface, but rather by scanning the semiconductor wafer. This is on the one hand very time-consuming, and on the other hand leads to problems with regard to the nanotopography in the scanning overlap region and also with regard to flatness (SFQRmax and edge roll off) in the outer region of the semiconductor wafer up to a distance of approximately 5 mm from the edge of the wafer. One possible cause is the intensified suction effect at the edge of the semiconductor wafer and therefore reduction of the etching medium, since work is carried out in vacuo. The required overlap during scanning has an adverse effect in particular on the nanotopography at the overlap positions. The larger the diameter of the nozzle which is used to supply the etching medium, the worse the deterioration is. However, for economic reasons the nozzle diameter cannot be chosen to be as small as may be desirable.
Consequently, the methods which are known in the prior art are unable to meet the geometry requirements for components with line widths of less than or equal to 65 nm, that is to say SFQRmax values of at most 65 nm. In this context, the most serious problems occur in the edge region of the semiconductor wafer, since the edge exclusion of currently 3 mm (for line widths of 90 nm) is reduced to 2 mm or 1 mm for the future line widths of 65 nm or less, and the partial sites are taken into account when assessing the flatness.
An additional problem arises in the case of so-called SOI wafers. These semiconductor wafers have a semiconductor layer which is situated on a surface of a carrier wafer (base wafer or handle wafer). The thickness of the semiconductor layer varies as a function of the components to be processed. In general, a distinction is drawn between the so-called “thin layers” (thickness less than 100 nm) and so-called “thick layers” (from 100 nm to approximately 80 μm). The carrier wafer may either be composed entirely of an electrically insulating material (e.g. glass, quartz, sapphire) or may, for example, be composed of a semiconductor material, preferably silicon, and is then merely separated from the semiconductor layer by an electrically insulating layer. The electrically insulating layer may comprise silicon oxide, for example.
SOI wafers are very important for the production of microelectronic components. The semiconductor layer of an SOI wafer has to have a very homogeneous thickness all the way into the outermost edge region. In particular in the case of semiconductor layers having a thickness of 100 nm or less, the transistor properties, such as e.g. the threshold voltage, vary very considerably in the case of inhomogeneous layer thicknesses. The absolute thickness tolerance for SOI wafers with thin and thick semiconductor layers depends on the layer thickness. The measurement method used to measure the layer thickness is preferably spectroscopic ellipsometry, reflectometry or interferometry.
In order to be able to integrate the maximum possible number of circuits, moreover, the required layer thickness homogeneity has to be ensured as close as possible to the edge of the front side. This in turn means a very small edge exclusion.
Methods for the aftertreatment of an SOI wafer with the aim of improving the layer thickness homogeneity are also known. They are generally local etching methods involving scanning the SOI wafer, a higher etching removal being provided at places where the layer thickness is higher: in accordance with US2004/0063329A1 the surface of the SOI wafer is scanned in a dry etching method by means of a nozzle which is used to locally supply a gaseous etching medium. EP488642A2 and EP511777A1 describe methods in which the semiconductor layer of the SOI wafer is exposed to an etching medium over its entire surface. However, the etching medium is locally activated by a laser beam or a light beam from a light source focused using an optical system, in a manner involving scanning the surface (photochemical etching).
All methods in which the surface of the semiconductor layer has to be scanned in order to achieve a locally different etching removal are very time-intensive and therefore cost-intensive. Moreover, the scanning requires a complex motion on the part of the light source or the nozzle, on the one hand, or the SOI wafer, on the other hand.
Moreover, additional inhomogeneities in the layer thickness occur particularly in the edge region of the wafer, i.e. in a region up to 5 mm away from the edge of the wafer, and in the regions in which the overlap occurs during scanning. Given a layer thickness of 520 nm, according to EP488642A2, a layer thickness homogeneity of 10 nm is achieved, without any details being given as to an edge exclusion. In accordance with EP511777A1, given a layer thickness of 108 nm, a layer thickness homogeneity of 8 nm is achieved, without any details being given as to an edge exclusion. Therefore, despite the complex methods disclosed by the art, the required layer thickness homogeneities are not achieved, in particular in the edge region of the SOI wafer.